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semiconductor technical data 1 rev 0 ? motorola, inc. 1996 9/96
highperformance silicongate cmos the mc54/74hc160a and hc162a are identical in pinout to the ls160 and ls162, respectively. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. the hc160a and hc162a are programmable bcd counters with asynchronous and synchronous reset inputs, respectively. ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2 to 6 v ? low input current: 1 m a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no. 7a ? chip complexity: 234 fets or 58.5 equivalent gates logic diagram pin 16 = v cc pin 8 = gnd 11 12 13 14 q0 q1 q2 q3 15 ripple carry out bcd outputs 3 4 5 6 p0 p1 p2 p3 2 clock reset load enable p enable t count enables present data inputs ???? ??? ? ???? device ???? ? ?? ? ???? count mode ????? ? ???? ????? reset mode ???? ???? hc160 ???? ???? bcd ????? ????? asynchronous ???? ???? hc162 ???? ???? bcd ????? ????? synchronous this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice.

pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 reset p0 clock gnd q1 q0 ripple carry out v cc p1 p2 p3 enable p q2 q3 enable t load d suffix soic package case 751b05 n suffix plastic package case 64808 ordering information mc54hcxxxaj mc74hcxxxan mc74hcxxxad ceramic plastic soic 1 16 1 16 j suffix ceramic package case 62010 1 16 inputs output clock reset* load enable p enable t q l x x x reset h l x x load preset data h h h h count h h l x no count h h x l no count function table * hc162a only. hc160a is an asynchronous reset device h = high level l = low level x = don't care
mc54/74hc160a mc54/74hc162a motorola highspeed cmos logic data dl129 e rev 6 2 ??????????????????????? ??????????????????????? maximum ratings* ??? ??? symbol ?????????????? ?????????????? parameter ?????? ?????? value ??? ??? unit ??? ??? v cc ?????????????? ?????????????? dc supply voltage (referenced to gnd) ?????? ?????? 0.5 to + 7.0 ??? ??? v ??? ??? v in ?????????????? ?????????????? dc input voltage (referenced to gnd) ?????? ?????? 0.5 to v cc + 0.5 ??? ??? v ??? ??? v out ?????????????? ?????????????? dc output voltage (referenced to gnd) ?????? ?????? 0.5 to v cc + 0.5 ??? ??? v ??? ??? i in ?????????????? ?????????????? dc input current, per pin ?????? ?????? 20 ??? ??? ma ??? ??? i out ?????????????? ?????????????? dc output current, per pin ?????? ?????? 25 ??? ??? ma ??? ??? i cc ?????????????? ?????????????? dc supply current, v cc and gnd pins ?????? ?????? 50 ??? ??? ma ??? ? ? ? ??? p d ?????????????? ? ???????????? ? ?????????????? power dissipation in still air, plastic or ceramic dip2 soic package2 ?????? ? ???? ? ?????? 750 500 ??? ? ? ? ??? mw ??? ??? t stg ?????????????? ?????????????? storage temperature ?????? ?????? 65 to + 150 ??? ??? c ??? ? ? ? ??? t l ?????????????? ? ???????????? ? ?????????????? lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) (ceramic dip) ?????? ? ???? ? ?????? 260 300 ??? ? ? ? ??? c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. 2derating e plastic dip: 10 mw/ c from 65 to 125 c ceramic dip: 10 mw/ c from 100 to 125 c soic package: 7 mw/ c from 65 to 125 c for high frequency or heavy load considerations, see chapter 2 of the motorola highspeed cmos data book (dl129/d). recommended operating conditions ???? ???? symbol ?????????????? ?????????????? parameter ??? ??? min ??? ??? max ??? ??? unit ???? ???? v cc ?????????????? ?????????????? dc supply voltage (referenced to gnd) ??? ??? 2.0 ??? ??? 6.0 ??? ??? v ???? ???? v in , v out ?????????????? ?????????????? dc input voltage, output voltage (referenced to gnd) ??? ??? 0 ??? ??? v cc ??? ??? v ???? ???? t a ?????????????? ?????????????? operating temperature, all package types ??? ??? 55 ??? ??? + 125 ??? ??? c ???? ? ?? ? ? ?? ? ???? t r , t f ?????????????? ? ???????????? ? ? ???????????? ? ?????????????? input rise and fall time v cc = 2.0 v (figure 1) v cc = 4.5 v v cc = 6.0 v ??? ? ? ? ? ? ? ??? 0 0 0 ??? ? ? ? ? ? ? ??? 1000 500 400 ??? ? ? ? ? ? ? ??? ns this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc54/74hc160a mc54/74hc162a highspeed cmos logic data dl129 e rev 6 3 motorola dc electrical characteristics (voltages referenced to gnd) ???? ???? sbl ????????? ????????? p ????????? ????????? t c di i ???? ???? v ????????? ????????? guaranteed limit ??? ??? ui ???? ? ?? ? ???? symbol ????????? ? ??????? ? ????????? parameter ????????? ? ??????? ? ????????? test conditions ???? ? ?? ? ???? v cc v ??? ? ?? ??? 55 to 25 c ???? ? ?? ? ???? 85 c ???? ? ?? ? ???? 125 c ??? ? ? ? ??? unit ???? ? ?? ? ? ?? ? v ih ????????? ? ??????? ? ? ??????? ? minimum highlevel input voltage ????????? ? ??????? ? ? ??????? ? v out = 0.1 v or v cc 0.1 v |i out | 20 m a ???? ? ?? ? ? ?? ? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? 1.5 2.1 3.15 4.2 ???? ? ?? ? ? ?? ? 1.5 2.1 3.15 4.2 ???? ? ?? ? ? ?? ? 1.5 2.1 3.15 4.2 ??? ? ? ? ? ? ? v ???? ? ?? ? ? ?? ? ???? v il ????????? ? ??????? ? ? ??????? ? ????????? maximum lowlevel input voltage ????????? ? ??????? ? ? ??????? ? ????????? v out = 0.1 v or v cc 0.1 v |i out | 20 m a ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 0.5 0.9 1.35 1.8 ???? ? ?? ? ? ?? ? ???? 0.5 0.9 1.35 1.8 ???? ? ?? ? ? ?? ? ???? 0.5 0.9 1.35 1.8 ??? ? ? ? ? ? ? ??? v ???? ? ?? ? ? ?? ? ???? v oh ????????? ? ??????? ? ? ??????? ? ????????? minimum highlevel output voltage ????????? ? ??????? ? ? ??????? ? ????????? v in = v ih or v il |i out | 20 m a ???? ? ?? ? ? ?? ? ???? 2.0 4.5 6.0 ??? ? ?? ? ?? ??? 1.9 4.4 5.9 ???? ? ?? ? ? ?? ? ???? 1.9 4.4 5.9 ???? ? ?? ? ? ?? ? ???? 1.9 4.4 5.9 ??? ? ? ? ? ? ? ??? v ???? ? ?? ? ???? ????????? ? ??????? ? ????????? ????????? ? ??????? ? ????????? v in = v ih or v il |i out | 2.4 m |i out | 4.0 ma |i out | 5.2 ma ???? ? ?? ? ???? 3.0 4.5 6.0 ??? ? ?? ??? 2.48 3.98 5.48 ???? ? ?? ? ???? 2.34 3.84 5.34 ???? ? ?? ? ???? 2.20 3.70 5.20 ??? ? ? ? ??? ???? ? ?? ? ???? v ol ????????? ? ??????? ? ????????? maximum lowlevel output voltage ????????? ? ??????? ? ????????? v in = v ih or v il |i out | 20 m a ???? ? ?? ? ???? 2.0 4.5 6.0 ??? ? ?? ??? 0.1 0.1 0.1 ???? ? ?? ? ???? 0.1 0.1 0.1 ???? ? ?? ? ???? 0.1 0.1 0.1 ??? ? ? ? ??? v ???? ? ?? ? ???? ????????? ? ??????? ? ????????? ????????? ? ??????? ? ????????? v in = v ih or v il |i out | 2.4 m |i out | 4.0 ma |i out | 5.2 ma ???? ? ?? ? ???? 3.0 4.5 6.0 ??? ? ?? ??? 0.26 0.26 0.26 ???? ? ?? ? ???? 0.33 0.33 0.33 ???? ? ?? ? ???? 0.40 0.40 0.40 ??? ? ? ? ??? ???? ???? i in ????????? ????????? maximum input leakage current ????????? ????????? v in = v cc or gnd ???? ???? 6.0 ??? ??? 0.1 ???? ???? 1.0 ???? ???? 1.0 ??? ??? m a ???? ? ?? ? ???? i cc ????????? ? ??????? ? ????????? maximum quiescent supply current (per package) ????????? ? ??????? ? ????????? v in = v cc or gnd i out = 0 m a ???? ? ?? ? ???? 6.0 ??? ? ?? ??? 4 ???? ? ?? ? ???? 40 ???? ? ?? ? ???? 160 ??? ? ? ? ??? m a note: information on typical parametric values can be found in chapter 2 of the motorola highspeed cmos data book (dl129/d).
mc54/74hc160a mc54/74hc162a motorola highspeed cmos logic data dl129 e rev 6 4 ac electrical characteristics (c l = 50 pf, input t r = t f = 6 ns) ???? ???? sbl ????????????????? ????????????????? p ???? ???? v ????????? ????????? guaranteed limit ??? ??? ui ???? ? ?? ? ???? symbol ????????????????? ? ??????????????? ? ????????????????? parameter ???? ? ?? ? ???? v cc v ??? ? ?? ??? 55 to 25 c ???? ? ?? ? ???? 85 c ???? ? ?? ? ???? 125 c ??? ? ? ? ??? unit ???? ? ?? ? ? ?? ? ???? f max ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? maximum clock frequency (50% duty cycle)* (figures 1 and 7) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 6.0 tbd 30 35 ???? ? ?? ? ? ?? ? ???? 4.8 tbd 24 28 ???? ? ?? ? ? ?? ? ???? 4.0 tbd 20 24 ??? ? ? ? ? ? ? ??? mhz ???? ? ?? ? ? ?? ? ???? t plh ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? maximum propagation delay, clock to q (figures 1 and 7) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 170 tbd 34 29 ???? ? ?? ? ? ?? ? ???? 215 tbd 43 37 ???? ? ?? ? ? ?? ? ???? 255 tbd 51 43 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t phl ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 205 tbd 41 35 ???? ? ?? ? ? ?? ? ???? 255 tbd 51 43 ???? ? ?? ? ? ?? ? ???? 310 tbd 62 53 ??? ? ? ? ? ? ? ??? ???? ? ?? ? ? ?? ? ???? t phl ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? maximum propagation delay, reset to q (hc160a only) (figures 2 and 7) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 210 tbd 42 36 ???? ? ?? ? ? ?? ? ???? 265 tbd 53 45 ???? ? ?? ? ? ?? ? ???? 315 tbd 63 54 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t plh ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? maximum propagation delay, enable t to ripple carry out (figures 3 and 7) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 160 tbd 32 27 ???? ? ?? ? ? ?? ? ???? 200 tbd 40 34 ???? ? ?? ? ? ?? ? ???? 240 tbd 48 41 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ? ?? ? ???? t phl ????????????????? ? ??????????????? ? ? ??????????????? ? ? ??????????????? ? ????????????????? ???? ? ?? ? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ? ?? ??? 195 tbd 39 33 ???? ? ?? ? ? ?? ? ? ?? ? ???? 245 tbd 49 42 ???? ? ?? ? ? ?? ? ? ?? ? ???? 295 tbd 59 50 ??? ? ? ? ? ? ? ? ? ? ??? ???? ? ?? ? ? ?? ? ? ?? ? t plh ????????????????? ? ??????????????? ? ? ??????????????? ? ? ??????????????? ? maximum propagation delay, clock to ripple carry out (figures 1 and 7) ???? ? ?? ? ? ?? ? ? ?? ? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ? ?? 175 tbd 35 30 ???? ? ?? ? ? ?? ? ? ?? ? 220 tbd 44 37 ???? ? ?? ? ? ?? ? ? ?? ? 265 tbd 53 45 ??? ? ? ? ? ? ? ? ? ? ns ???? ? ?? ? ? ?? ? ???? t phl ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 215 tbd 43 37 ???? ? ?? ? ? ?? ? ???? 270 tbd 54 46 ???? ? ?? ? ? ?? ? ???? 325 tbd 65 55 ??? ? ? ? ? ? ? ??? ???? ? ?? ? ? ?? ? ???? t phl ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? maximum propagation delay, reset to ripple carry out (hc160a only) (figures 2 and 7) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 220 tbd 44 37 ???? ? ?? ? ? ?? ? ???? 275 tbd 55 47 ???? ? ?? ? ? ?? ? ???? 330 tbd 66 56 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t tlh , t thl ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? maximum output transition time, any output (figures 1 and 7) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 75 27 15 13 ???? ? ?? ? ? ?? ? ???? 95 32 19 16 ???? ? ?? ? ? ?? ? ???? 110 36 22 19 ??? ? ? ? ? ? ? ??? ns ???? ???? c in ????????????????? ????????????????? maximum input capacitance ???? ???? e ??? ??? 10 ???? ???? 10 ???? ???? 10 ??? ??? pf * applies to noncascaded/nonsynchronously clocked configurations only. with synchronously cascaded counters, (1) clock to ripple carry out propagation delays, (2) enable t or enable p to clock setup times, and (3) clock to enable t or enable p hold times determine f max . however, if ripple carry out of each stage is tied to the clock of the next stage (nonsynchronously clocked), the f max in the table above is applicable. see applications information in this data sheet. notes: 1. for propagation delays with loads other than 50 pf, see c hapter 2 of the motorola highspeed cmos data book (dl129/d). 2. information on typical parametric values can be found in c hapter 2 of the motorola highspeed cmos data book (dl129/d). c pdiiici (ppk)* typical @ 25 c, v cc = 5.0 v f c pd power dissipation capacitance (per package)* 60 pf * used to determine the noload dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see chapter 2 of the motorola highspeed cmos data book (dl129/d).
mc54/74hc160a mc54/74hc162a highspeed cmos logic data dl129 e rev 6 5 motorola timing requirements (input t r = t f = 6 ns) ???? ???? sbl ????????????????? ????????????????? p ???? ???? v ????????? ????????? guaranteed limit ??? ??? ui ???? ? ?? ? ???? symbol ????????????????? ? ??????????????? ? ????????????????? parameter ???? ? ?? ? ???? v cc v ??? ? ?? ??? 55 to 25 c ???? ? ?? ? ???? 85 c ???? ? ?? ? ???? 125 c ??? ? ? ? ??? unit ???? ? ?? ? ? ?? ? ???? t su ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? minimum setup time, preset data inputs to clock (figure 5) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 150 tbd 30 26 ???? ? ?? ? ? ?? ? ???? 190 tbd 38 33 ???? ? ?? ? ? ?? ? ???? 225 tbd 45 38 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t su ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? minimum setup time, load to clock (figure 5) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 135 tbd 27 23 ???? ? ?? ? ? ?? ? ???? 170 tbd 34 29 ???? ? ?? ? ? ?? ? ???? 205 tbd 41 35 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t su ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? minimum setup time, reset to clock (hc162a only) (figure 4) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 160 tbd 32 27 ???? ? ?? ? ? ?? ? ???? 200 tbd 40 34 ???? ? ?? ? ? ?? ? ???? 240 tbd 48 41 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t su ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? minimum setup time, enable t or enable p to clock (figure 6) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 200 tbd 40 34 ???? ? ?? ? ? ?? ? ???? 250 tbd 50 43 ???? ? ?? ? ? ?? ? ???? 300 tbd 60 51 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t h ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? minimum hold time, clock to preset data inputs (figure 5) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 50 tbd 10 9 ???? ? ?? ? ? ?? ? ???? 65 tbd 13 11 ???? ? ?? ? ? ?? ? ???? 75 tbd 15 13 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ? ?? ? t h ????????????????? ? ??????????????? ? ? ??????????????? ? ? ??????????????? ? minimum hold time, clock to load (figure 5) ???? ? ?? ? ? ?? ? ? ?? ? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ? ?? 3 tbd 3 3 ???? ? ?? ? ? ?? ? ? ?? ? 3 tbd 3 3 ???? ? ?? ? ? ?? ? ? ?? ? 3 tbd 3 3 ??? ? ? ? ? ? ? ? ? ? ns ???? ? ?? ? ? ?? ? ???? t h ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? minimum hold time, clock to reset (hc162a only) (figure 4) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 3 tbd 3 3 ???? ? ?? ? ? ?? ? ???? 3 tbd 3 3 ???? ? ?? ? ? ?? ? ???? 3 tbd 3 3 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t h ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? minimum hold time, clock to enable t or enable p (figure 6) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 3 tbd 3 3 ???? ? ?? ? ? ?? ? ???? 3 tbd 3 3 ???? ? ?? ? ? ?? ? ???? 3 tbd 3 3 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t rec ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? minimum recovery time, reset inactive to clock (hc160a only) (figure 2) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 125 tbd 25 21 ???? ? ?? ? ? ?? ? ???? 155 tbd 31 26 ???? ? ?? ? ? ?? ? ???? 190 tbd 38 32 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t rec ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? minimum recovery time, load inactive to clock (figure 5) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 125 tbd 25 21 ???? ? ?? ? ? ?? ? ???? 155 tbd 31 26 ???? ? ?? ? ? ?? ? ???? 190 tbd 38 32 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t w ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? minimum pulse width, clock (figure 1) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 80 tbd 16 14 ???? ? ?? ? ? ?? ? ???? 100 tbd 20 17 ???? ? ?? ? ? ?? ? ???? 120 tbd 24 20 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t w ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? minimum pulse width, reset (hc160a only) (figure 2) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 80 tbd 16 14 ???? ? ?? ? ? ?? ? ???? 100 tbd 20 17 ???? ? ?? ? ? ?? ? ???? 120 tbd 24 20 ??? ? ? ? ? ? ? ??? ns ???? ? ?? ? ? ?? ? ???? t r , t f ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? maximum input rise and fall times (figure 1) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ??? ? ?? ? ?? ??? 1000 800 500 400 ???? ? ?? ? ? ?? ? ???? 1000 800 500 400 ???? ? ?? ? ? ?? ? ???? 1000 800 500 400 ??? ? ? ? ? ? ? ??? ns note: information on typical parametric values can be found in chapter 2 of the motorola highspeed cmos data book (dl129/d).
mc54/74hc160a mc54/74hc162a motorola highspeed cmos logic data dl129 e rev 6 6 function description the hc160a/162a are programmable 4bit synchronous counters that feature parallel load, synchronous or asynch- ronous reset, a carry output for cascading, and count enable controls. the hc160a and hc162a are bcd counters with asynch- ronous reset, and synchronous reset, respectively. inputs clock (pin 2) the internal flipflops toggle and the output count ad- vances with the rising edge of the clock input. in addition, control functions, such as resetting (hc162a) and loading occur with the rising edge of the clock input. preset data inputs p0, p1, p2, p3 (pins 3, 4, 5, 6) these are the data inputs for programmable counting. data on these pins may be synchronously loaded into the in- ternal flipflops and appear at the counter outputs. p0 (pin 3) is the leastsignificant bit and p3 (pin 6) is the mostsignifi- cant bit. outputs q0, q1, q2, q3 (pins 14, 13, 12, 11) these are the counter outputs (bcd or binary). q0 (pin 14) is the leastsignificant bit and q3 (pin 11) is the mostsignifi- cant bit. ripple carry out (pin 15) when the counter is in its maximum state (1001 for the bcd counters or 1111 for the binary counters), this output goes high, providing an external lookahead carry pulse that may be used to enable successive cascaded counters. rip- ple carry out remains high only during the maximum count state. the logic equation for this output is: ripple carry out = enable t q0 q1 q2 q3 for bcd counters hc160a and hc162a control functions resetting a low level on the reset pin (pin 1) resets the internal flip flops and sets the outputs (q0 through q3) to a low level. the hc160a resets asynchronously and the hc162a resets with the rising edge of the clock input (synchronous reset). loading with the rising edge of the clock, a low level on load (pin 9) loads the data from the preset data input pins (p0, p1, p2, p3) into the internal flipflops and onto the output pins, q0 through q3. the count function is disabled as long as load is low. although the hc160a and hc162a are bcd counters, they may be programmed to any state. if they are loaded with a state disallowed in bcd code, they will return to their nor- mal count sequence within two clock pulses (see the output state diagram). count enable/disable these devices have two countenable control pins: en- able p (pin 7) and enable t (pin 10). the devices count when these two pins and the load pin are high. the logic equation is: count enable = enable p enable t load the count is either enabled or disabled by the control in- puts according to table 1. in general, enable p is a count enable control; enable t is both a countenable and a ripplecarry output control. table 1. count enable/disable control inputs result at outputs load enable p enable t q0 q3 ripple carry out h h h count high when q0 q3 l h h no count g are maximum* x l h no count high when q0 q3 are maximum* x x l no count l * q0 through q3 are maximum for the hc160a and hc162a when q3 q2 q1 q0 = 1001. hc160a and hc162a bcd counters 01234 5 6 7 8 9 10 11 12 13 14 15 output state diagrams
mc54/74hc160a mc54/74hc162a highspeed cmos logic data dl129 e rev 6 7 motorola switching waveforms figure 1. figure 2. figure 3. figure 4. hc162a only figure 5. figure 6. test circuit figure 7. t r t f v cc gnd t thl t tlh any output 90% 50% 10% 90% 50% 10% clock t plh t phl 50% t phl v cc gnd v cc gnd any output clock reset 50% 50% t rec t r t f v cc gnd t phl t plh 90% 50% 10% 90% 50% 10% t thl t tlh enable t ripple carry out clock reset 50% t su v cc gnd 50% inputs p0, p1, p2, p3 50% v cc gnd v cc gnd gnd 50% 50% load clock v cc gnd v cc gnd enable t or enable p 50% 50% clock * includes all probe and jig capacitance c l * test point device under test output v cc t w 1/fmax t w t h valid t su t h t su t h t rec valid t su t h
mc54/74hc160a mc54/74hc162a motorola highspeed cmos logic data dl129 e rev 6 8 mc54hc160a mc74hc160a ? bcd counter with asynchronous reset p0 p1 p2 p3 enable p enable t reset clock load r c t0 r c c load load p0 q0 q0 q1 q2 q3 ripple carry out v cc = pin 16 gnd = pin 8 14 the flipflops shown in the circuit diagrams are toggleenable flipflops. a toggle enable flipflop is a combination of a d flipflop and a t flipflop. when loading data from preset inputs p0, p1, p2, and p3, the load signal is used to disable the toggle input (tn) of the flipflop. the logic level at the pn input is then clocked to the q output of the flipflop on the next rising edge of the clock. a logic zero on the reset device input forces the internal clock (c) high and resets the q output of the flipflop low. c load load q0 q1 q1 q2 q2 q3 q3 t1 r c c load load p1 t2 r c c load load p2 t3 r c c load load p3 13 12 11 15 3 4 5 6 7 10 1 2 3
mc54/74hc160a mc54/74hc162a highspeed cmos logic data dl129 e rev 6 9 motorola hc160a, hc162a timing diagram sequence illustrated in waveforms: 1. reset outputs to zero. 2. preset to bcd seven. 3. count to eight, nine, zero, one, two, and three. 4. inhibit. reset (hc160a) reset (hc162a) load p0 p1 p2 p3 clock (hc160a) clock (hc162a) enable p enable t q0 q1 q2 q3 ripple carry out (asynchronous) (synchronous) 789012 3 reset load count enables outputs preset data inputs inhibit count
mc54/74hc160a mc54/74hc162a motorola highspeed cmos logic data dl129 e rev 6 10 mc54hc160a mc74hc160a ? bcd counter with synchronous reset p0 p1 p2 p3 enable p enable t reset clock load r c t0 r c c load load p0 q0 q0 q1 q2 q3 ripple carry out v cc = pin 16 gnd = pin 8 14 the flipflops shown in the circuit diagrams are toggleenable flipflops. a toggle enable flipflop is a combination of a d flipflop and a t flipflop. when loading data from preset inputs p0, p1, p2, and p3, the load signal is used to disable the toggle input (tn) of the flipflop. the logic level at the pn input is then clocked to the q output of the flipflop on the next rising edge of the clock. a logic zero on the reset device input forces the internal clock (c) high and resets the q output of the flipflop low. c load load q0 q1 q1 q2 q2 q3 q3 t1 r c c load load p1 t2 r c c load load p2 t3 r c c load load p3 13 12 11 15 3 4 5 6 7 10 1 2 3
mc54/74hc160a mc54/74hc162a highspeed cmos logic data dl129 e rev 6 11 motorola inputs outputs to more significant stages load h = count l = disable h = count l = disable reset clock load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load reset clock enable p enable t typical applications cascading nbit synchronous counters note: when used in these cascaded configurations the clock f max guaranteed limits may not apply. actual performance will depend on number of stages. this limitation is due to set up times between enable (port) and clock. nibble ripple counter load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out inputs outputs inputs outputs inputs inputs inputs outputs outputs outputs to more significant stages load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out
mc54/74hc160a mc54/74hc162a motorola highspeed cmos logic data dl129 e rev 6 12 modulo5 counter output optional buffer for noise rejection other inputs reset hc162a q0 q1 q2 q3 typical application the hc162a facilitates designing counters of any modulus with minimal external logic. the output is glitchfree due to the synchronous reset.
mc54/74hc160a mc54/74hc162a highspeed cmos logic data dl129 e rev 6 13 motorola outline dimensions j suffix ceramic package case 62010 issue v n suffix plastic package case 64808 issue r 19.05 6.10 e 0.39 1.40 0.21 3.18 19.93 7.49 5.08 0.50 1.65 0.38 4.31 0 0.51 15 1.01 1.27 bsc 2.54 bsc 7.62 bsc min min max max inches millimeters dim 0.750 0.240 e 0.015 0.055 0.008 0.125 0.785 0.295 0.200 0.020 0.065 0.015 0.170 0.050 bsc 0.100 bsc 0.300 bsc a b c d e f g j k l m n 0 0.020 15 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dim f may narrow to 0.76 (0.030) where the lead enters the ceramic body. 18 9 16 a b c k n g e f d 16 pl t seating plane m l j 16 pl 0.25 (0.010) t a m s 0.25 (0.010) t b m s min min max max inches millimeters dim a b c d f g h j k l m s 18.80 6.35 3.69 0.39 1.02 0.21 2.80 7.50 0 0.51 19.55 6.85 4.44 0.53 1.77 0.38 3.30 7.74 10 1.01 0.740 0.250 0.145 0.015 0.040 0.008 0.110 0.295 0 0.020 0.770 0.270 0.175 0.021 0.070 0.015 0.130 0.305 10 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. 2.54 bsc 1.27 bsc 0.100 bsc 0.050 bsc a b 18 9 16 f h g d 16 pl s c t seating plane k j m l ta 0.25 (0.010) m m 0.25 (0.010) t b a m s s min min max max millimeters inches dim a b c d f g j k m p r 9.80 3.80 1.35 0.35 0.40 0.19 0.10 0 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 7 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 7 0.244 0.019 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 1 8 9 16 a b d 16 pl k c g t seating plane r x 45 m j f p 8 pl 0.25 (0.010) b m m d suffix plastic soic package case 751b05 issue j
mc54/74hc160a mc54/74hc162a motorola highspeed cmos logic data dl129 e rev 6 14 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 20912; phoenix, arizona 85036. 18004412447 or 6023035454 3142 tatsumi kotoku, tokyo 135, japan. 038135218315 mfax : rmfax0@email.sps.mot.com t ouchtone 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 mc74hc160a/d
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